High-speed, low-power analog-to-digital converters (ADCs) are widely used in numerous applications, for example in portable wireless communications devices. The general architecture of a typical ADC is shown in FIG. 3. An analog input signal IA is provided to a track-and-hold (or, sample-and-hold) circuit that receives IA and samples the voltage of that signal at regular intervals. These sample voltages are each held for a period, and provided serially to form an output signal IS that is provided as an output of the track-and-hold circuit and as an input to the following stage, a quantizer. The quantizer converts the values of the voltage levels of IS to a digital signal, that it outputs as OD.
The requirement for ever improved performance in the commercial world of technology results in a corresponding demand for ever improved performance of ADCs. Generally, the performance of high-speed ADC is limited by the performance of its track-and-hold circuit. U.S. Pat. No. 6,489,814, which issued on Dec. 3, 2002, to Gian Hoogzaad et al., discloses an exemplary prior art track-and-hold circuit that attempts to reduce excess currents flowing onto the hold capacitor using a feedback connection. However, prior art track-and-hold circuits still suffer from problems such as harmonic distortion, that adversely affects performance of the ADC.
There is thus a need for a way of improving the performance of ADC track-and-hold circuits.